Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5 D semiconductor packages.

Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5 D semiconductor packages.

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.

Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. A hybrid bond is formed by evaporating the droplet and a subsequent anneal.

A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the IC die structure and a bonding surface of the substrate structure during placement. The inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. Inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting IC die edges may also be non-orthogonal.

A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.

A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

In accordance with an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first semiconductor wafer and a second semiconductor wafer, wherein the second semiconductor wafer disposed on the first semiconductor wafer. The first semiconductor wafer includes a first substrate, a first metallization layer, a first dielectric layer, a first magnetic structure, and a first metal pad. The second semiconductor wafer includes a second substrate, a second metallization layer, a second dielectric layer, a second magnetic structure, and a second metal pad. The first magnetic structure is aligned with and in direct contact with the second magnetic structure, and a top surface of the first dielectric layer is in direct contact with a top surface of the second dielectric layer.