An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

There is provided a method of bonding substrates to each other, which includes: holding a first substrate on a lower surface of a first holding part; adjusting a temperature of a second substrate by a temperature adjusting part to become higher than a temperature of the first substrate; holding the second substrate on an upper surface of a second holding part; inspecting a state of the second substrate by imaging a plurality of reference points of the second substrate with a first imaging part, measuring positions of the reference points, and comparing a measurement result with a predetermined permissible range; and pressing a central portion of the first substrate with a pressing member, bringing the central portion of the first substrate into contact with a central portion of the second substrate, and sequentially bonding the first substrate and the second substrate.

There is provided a method of bonding substrates to each other, which includes: holding a first substrate on a lower surface of a first holding part; adjusting a temperature of a second substrate by a temperature adjusting part to become higher than a temperature of the first substrate; holding the second substrate on an upper surface of a second holding part; inspecting a state of the second substrate by imaging a plurality of reference points of the second substrate with a first imaging part, measuring positions of the reference points, and comparing a measurement result with a predetermined permissible range; and pressing a central portion of the first substrate with a pressing member, bringing the central portion of the first substrate into contact with a central portion of the second substrate, and sequentially bonding the first substrate and the second substrate.

A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures. Deformation of the conductive material of the contact structures through creep pushes the material into the openings from the bottom up, thereby bringing the contact patches into mutual and conductive contact.

A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures. Deformation of the conductive material of the contact structures through creep pushes the material into the openings from the bottom up, thereby bringing the contact patches into mutual and conductive contact.

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.

A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.

A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.