Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

A substrate bonding method includes a plasma processing step of processing a bonding surface of each of the substrates with a rare gas plasma which is a plasma of a rare gas, processing the bonding surface of each of the substrates processed with the rare gas plasma with a hydrogen plasma which is a plasma of hydrogen, and processing the bonding surface of each of the substrates processed with the hydrogen plasma with a nitrogen plasma which is a plasma of nitrogen and a substrate bonding step of bonding two substrates by bringing the bonding surfaces of the two substrates into contact with each other such that copper pads of the two substrates face each other and insulating films of the two substrates face each other after the plasma processing step.

Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

Provided is a semiconductor package including a lower structure, an upper structure on the lower structure, and a first interfacial layer interposed between the lower structure and the upper structure. The lower structure includes a first semiconductor substrate, a first pad on the first semiconductor substrate, and a first insulating layer surrounding the first pad on the first semiconductor substrate. The upper structure includes a second semiconductor substrate, a second pad on the second semiconductor substrate, and a second insulating layer surrounding the second pad on the second semiconductor substrate. The first interfacial layer includes a first self-assembled monolayer bonded to the first insulating layer, and a second self-assembled monolayer bonded to the second insulating layer.