A semiconductor package includes a lower semiconductor chip having a first surface and a second surface, an upper semiconductor chip on the first surface, a first insulating layer between the first surface and the upper semiconductor chip, a second insulating layer between the first insulating layer and the upper semiconductor chip, and a connection structure penetrating the first insulating layer and the second insulating layer and being connected to the lower semiconductor chip and the upper semiconductor chip. The connection structure includes a first connecting portion and a second connecting portion, which are respectively disposed in the first insulating layer and the second insulating layer. A width of the second connecting portion is greater than a width of the first connecting portion. A thickness of the second connecting portion is greater than a thickness of the first connecting portion.

A semiconductor package includes a lower semiconductor chip having a first surface and a second surface, an upper semiconductor chip on the first surface, a first insulating layer between the first surface and the upper semiconductor chip, a second insulating layer between the first insulating layer and the upper semiconductor chip, and a connection structure penetrating the first insulating layer and the second insulating layer and being connected to the lower semiconductor chip and the upper semiconductor chip. The connection structure includes a first connecting portion and a second connecting portion, which are respectively disposed in the first insulating layer and the second insulating layer. A width of the second connecting portion is greater than a width of the first connecting portion. A thickness of the second connecting portion is greater than a thickness of the first connecting portion.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

A metal-dielectric bonding method includes providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes: a first semiconductor layer including a complementary metal-oxide-semiconductor device, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, the first metal layer having a metal bonding surface. The metal bonding surface is planarized and a plasma treatment is applied thereto. The second semiconductor structure includes a second semiconductor layer including a pixel wafer, and a second dielectric layer on the second semiconductor layer, the second dielectric layer having a dielectric bonding surface. The dielectric bonding surface is planarized and a plasma treatment is applied thereto. The first and second semiconductor structures are bonded together by bonding the metal bonding surface with the dielectric bonding surface.

A metal-dielectric bonding method includes providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes: a first semiconductor layer including a complementary metal-oxide-semiconductor device, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, the first metal layer having a metal bonding surface. The metal bonding surface is planarized and a plasma treatment is applied thereto. The second semiconductor structure includes a second semiconductor layer including a pixel wafer, and a second dielectric layer on the second semiconductor layer, the second dielectric layer having a dielectric bonding surface. The dielectric bonding surface is planarized and a plasma treatment is applied thereto. The first and second semiconductor structures are bonded together by bonding the metal bonding surface with the dielectric bonding surface.

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.