A box for a microelectronic device includes a first portion and a second portion able to be assembled in order to define, in an assembled position, a housing space for the microelectronic device. A face of the first portion is facing a face of the second portion in the assembled position. The first zones facing the faces form an interface for attaching the first portion and second portion. The second zones face faces forming a cavity for receiving the microelectronic device. At least one among the first portion and the second portion includes at least one element for electrical connection. The first portion and the second portion can apply at least one connection pad of the microelectronic device on the element for connection in the assembled position.

A box for a microelectronic device includes a first portion and a second portion able to be assembled in order to define, in an assembled position, a housing space for the microelectronic device. A face of the first portion is facing a face of the second portion in the assembled position. The first zones facing the faces form an interface for attaching the first portion and second portion. The second zones face faces forming a cavity for receiving the microelectronic device. At least one among the first portion and the second portion includes at least one element for electrical connection. The first portion and the second portion can apply at least one connection pad of the microelectronic device on the element for connection in the assembled position.

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.

A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.

A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.