A method for self-assembling microelectronic components includes providing a self-aligning substrate having protrusions, each having a thickness greater than 1 μm and an upper face and flanks, the upper face and the flanks being hydrophobic. The method also includes providing dies, each die having a first face and a second hydrophilic face, and providing a self-assembling substrate. Finally, the method includes obtaining, by capillary effect, the self-alignment of each die through the first face thereof on a protrusion of the self-aligning substrate, then obtaining the assembly of the dies through the second hydrophilic face thereof on the self-assembling substrate by direct adhesion. Such a method has application in the industrial production of 3D integrated circuits.

A method for self-assembling microelectronic components includes providing a self-aligning substrate having protrusions, each having a thickness greater than 1 μm and an upper face and flanks, the upper face and the flanks being hydrophobic. The method also includes providing dies, each die having a first face and a second hydrophilic face, and providing a self-assembling substrate. Finally, the method includes obtaining, by capillary effect, the self-alignment of each die through the first face thereof on a protrusion of the self-aligning substrate, then obtaining the assembly of the dies through the second hydrophilic face thereof on the self-assembling substrate by direct adhesion. Such a method has application in the industrial production of 3D integrated circuits.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

A method for directly bonding a first and a second substrate. The method comprises removing surface oxide layers from bonding faces of the first and of the second substrate, and hydrogen passivation of the bonding faces, then, in a vacuum, electron impact hydrogen desorption on the bonding faces followed by placement of the bonding faces in intimate contact with one another.

Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

A method is presented for fabricating a substrate comprised of a compound semiconductor. The method includes: growing a sacrificial layer onto a parent substrate; growing an epitaxial template layer on the sacrificial layer; removing the template layer from the parent substrate using an epitaxial lift-off procedure; and bonding the removed template layer to a host substrate using Van der Waals forces and thereby forming a compound semiconductor substrate.

Various embodiments of the present disclosure are directed towards a method for forming a microelectromechanical systems (MEMS) device. The method includes forming a filter stack over a carrier substrate. The filter stack comprises a particle filter layer having a particle filter. A support structure layer is formed over the filter stack. The support structure layer is patterned to define a support structure in the support structure layer such that the support structure has one or more segments. The support structure is bonded to a MEMS structure.

Various embodiments of the present disclosure are directed towards a method for forming a microelectromechanical systems (MEMS) device. The method includes forming a filter stack over a carrier substrate. The filter stack comprises a particle filter layer having a particle filter. A support structure layer is formed over the filter stack. The support structure layer is patterned to define a support structure in the support structure layer such that the support structure has one or more segments. The support structure is bonded to a MEMS structure.

The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, a second insulating layer positioned above the first insulating layer, a plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and an alleviation structure positioned between the first insulating layer and the second insulating layer. The alleviation structure includes a first connecting interlayer respectively electrically coupled to the plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and a plurality of alleviation structures positioned between the plurality of first conductive features in the first insulating layer and the plurality of first conductive features in the second insulating layer, wherein a porosity of the plurality of alleviation structures is between about 25% and about 100%.