Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and an insulating structure extending vertically through the memory stack, the first semiconductor layer, and the second semiconductor layer.

A semiconductor package includes a substrate, an interposer, a primary component layer, a first redistribution layer, multiple solder bumps and a first hybrid bonding structure. The interposer is disposed above the substrate and includes multiple TSV sets. The primary component layer is disposed above the interposer and includes multiple first chips and a first molding material that fills the space between the multiple first chips. The first redistribution layer is disposed between the primary component layer and the interposer and includes at least one portion of an antenna structure. The plurality of solder bumps is disposed between the substrate and the interposer. The first hybrid bonding structure is disposed between the multiple first chips and the multiple TSV sets for electrical connection in between and includes multiple connection components that respectively apply bonding of multiple metal pieces in between.

A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

A direct bonding method for infrared focal plane arrays, includes steps of depositing a thin adhesion layer on infrared radiation detecting material, removing a portion of the thin adhesion layer with a chemical-mechanical polishing process, forming a bonding layer at a bonding interface, and bonding the infrared radiation detecting material to a silicon wafer with the thin adhesion layer as a bonding layer. The thin adhesion layer may include SiO.sub.x, where x ranges between 1.0 and 2.0. The thickness of the thin adhesion layer to form the bonding layer is 500 angstrom or less.

Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.

A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer overlapping the first semiconductor layer, and a wiring structure arranged between them. The second semiconductor layer is provided with p-type MIS transistor. A crystal structure of the first semiconductor layer has a first crystal orientation and a second crystal orientation in direction along a principal surface of the first semiconductor layer. A Young's modulus of the first semiconductor layer in a direction along the first crystal orientation is higher than that in a direction along the second crystal orientation. An angle formed by the first crystal orientation and a direction in which a source and a drain of the p-type MIS transistor are arranged is more than 30 degrees and less than 60 degrees, and an angle formed by the second crystal orientation and that direction is 0 degrees or more and 30 degrees or less.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.