The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.

The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.

A method of hybridizing an FPA having an IR component and a ROIC component and interconnects between the two components, includes the steps of: providing an IR detector array and a Si ROIC; depositing a dielectric layer on both the IR detector array and on the Si ROIC; patterning the dielectric on both components to create openings to expose contact areas on each of the IR detector array and the Si ROIC; depositing indium to fill the openings on both the IR detector array and the Si ROIC to create indium bumps, the indium bumps electrically connected to the contact areas of the IR detector array and the Si ROIC respectively, exposed on a top surface of the IR detector array and the Si ROIC; activating exposed dielectric layers on the IR detector array and the Si ROIC in a plasma; and closely contacting the indium bumps of the IR detector array and the Si ROIC by bonding together the exposed dielectric surfaces of the IR detector array and the Si ROIC. Another exemplary method provides a pillar support of the indium bumps on the IR detector array rather than a full dielectric layer support. Another exemplary method includes a surrounding dielectric edge support between the IR detector array and the Si ROIC with the pillar supports.

A method of hybridizing an FPA having an IR component and a ROIC component and interconnects between the two components, includes the steps of: providing an IR detector array and a Si ROIC; depositing a dielectric layer on both the IR detector array and on the Si ROIC; patterning the dielectric on both components to create openings to expose contact areas on each of the IR detector array and the Si ROIC; depositing indium to fill the openings on both the IR detector array and the Si ROIC to create indium bumps, the indium bumps electrically connected to the contact areas of the IR detector array and the Si ROIC respectively, exposed on a top surface of the IR detector array and the Si ROIC; activating exposed dielectric layers on the IR detector array and the Si ROIC in a plasma; and closely contacting the indium bumps of the IR detector array and the Si ROIC by bonding together the exposed dielectric surfaces of the IR detector array and the Si ROIC. Another exemplary method provides a pillar support of the indium bumps on the IR detector array rather than a full dielectric layer support. Another exemplary method includes a surrounding dielectric edge support between the IR detector array and the Si ROIC with the pillar supports.

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

A method of hybridizing an FPA having an IR component and a ROIC component and interconnects between the two components, includes the steps of: providing an IR detector array and a Si ROIC; depositing a dielectric layer on both the IR detector array and on the Si ROIC; patterning the dielectric on both components to create openings to expose contact areas on each of the IR detector array and the Si ROIC; depositing indium to fill the openings on both the IR detector array and the Si ROIC to create indium bumps, the indium bumps electrically connected to the contact areas of the IR detector array and the Si ROIC respectively, exposed on a top surface of the IR detector array and the Si ROIC; activating exposed dielectric layers on the IR detector array and the Si ROIC in a plasma; and closely contacting the indium bumps of the IR detector array and the Si ROIC by bonding together the exposed dielectric surfaces of the IR detector array and the Si ROIC. Another exemplary method provides a pillar support of the indium bumps on the IR detector array rather than a full dielectric layer support. Another exemplary method includes a surrounding dielectric edge support between the IR detector array and the Si ROIC with the pillar supports.

A method of hybridizing an FPA having an IR component and a ROIC component and interconnects between the two components, includes the steps of: providing an IR detector array and a Si ROIC; depositing a dielectric layer on both the IR detector array and on the Si ROIC; patterning the dielectric on both components to create openings to expose contact areas on each of the IR detector array and the Si ROIC; depositing indium to fill the openings on both the IR detector array and the Si ROIC to create indium bumps, the indium bumps electrically connected to the contact areas of the IR detector array and the Si ROIC respectively, exposed on a top surface of the IR detector array and the Si ROIC; activating exposed dielectric layers on the IR detector array and the Si ROIC in a plasma; and closely contacting the indium bumps of the IR detector array and the Si ROIC by bonding together the exposed dielectric surfaces of the IR detector array and the Si ROIC. Another exemplary method provides a pillar support of the indium bumps on the IR detector array rather than a full dielectric layer support. Another exemplary method includes a surrounding dielectric edge support between the IR detector array and the Si ROIC with the pillar supports.

A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.