A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

An apparatus includes a product substrate having a transfer surface, and a semiconductor die defined, at least in part, by a first surface adjoined to a second surface that extends in a direction transverse to the first surface. The transfer surface includes ripples in a profile thereof such that an apex on an individual ripple is a point on a first plane and a trough on the individual ripple is a point on a second plane. The semiconductor die is disposed on the transfer surface between the first plane and the second plane such that the second surface of the semiconductor die extends transverse to the first plane and the second plane.

A method of using an optoelectronic semiconductor stamp to manufacture an optoelectronic semiconductor device comprises the following steps: a preparation step: preparing at least one optoelectronic semiconductor stamp group and a target substrate, wherein each optoelectronic semiconductor stamp group comprises at least one optoelectronic semiconductor stamp, each optoelectronic semiconductor stamp comprises a plurality of optoelectronic semiconductor components disposed on a heat conductive substrate, each optoelectronic semiconductor component has at least one electrode, and the target substrate has a plurality of conductive portions; an align-press step: aligning and attaching at least one optoelectronic semiconductor stamp to the target substrate, so that the electrodes are pressed on the corresponding conductive portions; and a bonding step: electrically connecting the electrodes to the corresponding conductive portions.

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.

A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises connection terminals between a first die and a second die. The first die has signal and peripheral regions and includes first vias on the peripheral region. The second die is on the first die and has second vias on positions that correspond to the first vias. The connection terminals connect the second vias to the first vias. The peripheral region includes first regions adjacent to corners of the first die and second regions adjacent to lateral surfaces of the first die. The connection terminals include first connection terminals on the first regions and second connection terminals on the second regions. A sum of areas of the first connection terminals per unit area on the first regions is greater than that of areas of the second connection terminals per unit area on the second regions.

An interposer may include a first metal trace located on a first dielectric layer, a second dielectric layer located on the first dielectric layer, a line-shaped via located in the second dielectric layer and connected to the first metal trace, and a second metal trace located on the second dielectric layer and connected to the line-shaped via.