Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.

A transferring method, a manufacturing method, a device and an electronic apparatus of micro-LED. The method for transferring micro-LED, comprises: forming micro-LEDs (202) on a laser-transparent original substrate (201), providing an anisotropic conductive layer (203) on a receiving substrate (204), bringing the micro-LEDs (202) into contact with the anisotropic conductive layer (203) on the receiving substrate (204), irradiating the original substrate (201) with laser from the original substrate side to lift-off the micro-LEDs (202) from the original substrate (201), and processing the anisotropic conductive layer (203), to electrically connect the micro-LEDs (202) with the pads (205′) on the receiving substrate (204).

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.

A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.

Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.

Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials with enhanced stability at room temperature.

A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.