A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

An electronic device includes a first structure body and a second structure body. The first structure body includes a first base body, a first bonding electrode and a first hard part. The second structure body includes a second base body, and a second bonding electrode. The first bonding electrode and the second bonding electrode are bonded to each other between the first base body and the second base body. The first hard part is located between the first base body and the second base body. The first hard part is positioned within an area in which the first bonding electrode is located when viewed along a first direction. The first direction is from the first base body toward the first bonding electrode. The first hard part has a higher hardness than the first bonding electrode.

A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.

In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.

A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

A semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed over the first semiconductor chip; and a bump structure interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core portion and a shell portion, the shell portion surrounding all side ails of the core portion, and wherein the shell portion has a higher melting point than the core portion.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.