A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

An adhesive for semiconductors, the adhesive containing a thermoplastic resin, a thermosetting resin, a curing agent having a reactive group, and a flux compound having an acid group. The adhesive has a calorific value of 20 J/g or less at 60° C. to 155° C. on a DSC curve, which is obtained by differential scanning calorimetry involving heating the adhesive at a rate of temperature increase of 10° C./min.

A conductive adhesive composition, the composition containing: (A) conductive particles; (B) a thermosetting resin; and (C) a flux activator. The conductive particles contain a metal having a melting point of 200° C. or lower. In a volume-based cumulative particle size distribution of the conductive particles, a cumulative 50% particle diameter D50 is 3 to 10 μm, and a cumulative 10% particle diameter D10 is 2.4 μm or more. The flux activator contains a compound having a hydroxyl group and a carboxyl group.

A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.

The present disclosure relates to a backplane, a backlight source, a display device, and a manufacturing method of the backplane. The backplane includes: a substrate; a plurality of barriers disposed on a surface of the substrate; and a first metal layer disposed on the surface of the substrate and including a plurality of metal patterns spaced apart by the plurality of barriers, wherein the barrier and the metal pattern are connected by a concave-convex mating structure.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Provided a semiconductor chip bonding apparatus including a body, a heater disposed on a lower surface of the body, a collet disposed on a lower surface of the heater, and a head disposed on a lower surface of the collet, the head has a rectangular plate shape, a lower surface and side surfaces of the head are exposed, an upper surface of the head is in contact with the lower surface of the collet, an area of the upper surface of the head is smaller than an area of the lower surface of the collet, the head includes a central section including a recess, and an outer surface constituting a part of the side surfaces of the head, and a peripheral section connected to the recess and disposed on each corners of the head, and a thermal conductivity of the peripheral section is different from that of the central section.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.