An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.

A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put the longitudinal portions of the components in the through holes. In addition, the method includes connecting a substrate to the components which have their longitudinal portions in the through holes and removing the positioning plate.

An apparatus for bonding a semiconductor chip to a package substrate, the apparatus comprising: a die-bonding unit configured to attach the semiconductor chip to the package substrate; a load-measuring unit installed at the die-bonding unit, the load-measuring unit including a panel having a plurality of regions and a plurality of load-measuring members with at least one load-measuring member arranged in each of the regions of the panel to measure load values applied to each of the regions; and a controller configured to determine a load and a flatness of the semiconductor chip based on the load values measured by the load-measuring members.

A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.

The invention relates to a transponder layer (10), in particular for producing a chip card, having an antenna substrate (12), which, on an antenna side (11), is equipped with an antenna (14) formed from a wire conductor (13), and has a chip accommodation which is formed by a recess in the antenna substrate and in which a chip (21) is accommodated, wherein wire conductor ends, which serve to form terminal ends (15) of the antenna, are formed at a bottom (20) of the chip accommodation which is recessed with respect to the rear side (26) of the antenna substrate (12), and the chip is accommodated in the chip accommodation in such a manner that terminal contacts (22) arranged on a contact side (36) of the chip are contacted with flat contact portions (19) of the terminal ends (15), and the chip is arranged with the rear side (27) of its semiconductor body (28) facing the terminal contacts substantially flush with the rear side of the antenna substrate. Furthermore, the invention relates to a method for producing a transponder layer.