A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 μm.

An object of the present invention is to provide a semiconductor device that has high electromagnetic wave shielding properties while exhibiting good heat dissipation. The semiconductor device according to the present invention includes a semiconductor package bonded onto a circuit board, an electromagnetic wave absorbing layer covering surfaces of the semiconductor package other than a surface bonded to the circuit board, and an electromagnetic wave reflecting layer covering the electromagnetic wave absorbing layer on a side remote from the semiconductor package, in which the electromagnetic wave absorbing layer is made of resin containing magnetic particles or carbon, and the electromagnetic wave reflecting layer is made of resin containing conductive particles.

An object of the present invention is to provide a semiconductor device that has high electromagnetic wave shielding properties while exhibiting good heat dissipation. The semiconductor device according to the present invention includes a semiconductor package bonded onto a circuit board, an electromagnetic wave absorbing layer covering surfaces of the semiconductor package other than a surface bonded to the circuit board, and an electromagnetic wave reflecting layer covering the electromagnetic wave absorbing layer on a side remote from the semiconductor package, in which the electromagnetic wave absorbing layer is made of resin containing magnetic particles or carbon, and the electromagnetic wave reflecting layer is made of resin containing conductive particles.

The invention relates to a power module. The power module has at least one power semiconductor and at least one further electronic component. The power module has a housing which is formed by a shaped body and is formed by an encapsulation compound. According to the invention, the housing is formed in at least two levels. At least one power semiconductor component is arranged in a first level and the at least one further electronic component is arranged in the second level. At least one electrically conductive layer, which forms an electrically conductive connecting structure, is formed on a surface of an inner boundary of the power module which extends between the levels. The connecting structure is applied directly to the surface. The at least one further electronic component is electrically conductively connected, in particular soldered or sintered, to the wiring structure. The power semiconductor component in the first level is electrically connected to the further component in the second level by means of the connecting structure.

The invention relates to a power module. The power module has at least one power semiconductor and at least one further electronic component. The power module has a housing which is formed by a shaped body and is formed by an encapsulation compound. According to the invention, the housing is formed in at least two levels. At least one power semiconductor component is arranged in a first level and the at least one further electronic component is arranged in the second level. At least one electrically conductive layer, which forms an electrically conductive connecting structure, is formed on a surface of an inner boundary of the power module which extends between the levels. The connecting structure is applied directly to the surface. The at least one further electronic component is electrically conductively connected, in particular soldered or sintered, to the wiring structure. The power semiconductor component in the first level is electrically connected to the further component in the second level by means of the connecting structure.

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm.sup.2. A ratio of a coefficient of thermal expansion of the substrate (CTE.sub.sub) to a coefficient of thermal expansion of the integrated circuit die (CTE.sub.die) is at least about 3:1. A method of manufacturing an IC package is also disclosed.