Patent classifications
H01L2224/8121
Method for fabricating LED module using transfer tape
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips.
Micro-LED array transfer
Methods of transferring micro-array LEDs of various colors onto a surface of a display substrate are provided. The transferring includes releasing micro-LEDs of a specific color from a structure that includes a releasable material onto a display substrate. The releasable material may be a laser ablatable material or a material that is readily dissolved in a specific etchant.
Micro-LED array transfer
Methods of transferring micro-array LEDs of various colors onto a surface of a display substrate are provided. The transferring includes releasing micro-LEDs of a specific color from a structure that includes a releasable material onto a display substrate. The releasable material may be a laser ablatable material or a material that is readily dissolved in a specific etchant.
Cavity based feature on chip carrier
A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.
Cavity based feature on chip carrier
A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.
ACRYLIC COMPOSITION FOR ENCAPSULATION, SHEET MATERIAL, LAMINATED SHEET, CURED OBJECT, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE
The acrylic composition for sealing contains an acrylic compound, a polyphenylene ether resin including a radical-polymerizable substituent at a terminal, an inorganic filler, and a thermal radical polymerization initiator.
LED MODULE AND METHOD FOR FABRICATING THE SAME
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips.
SYSTEM AND METHOD FOR DEPOSITING UNDERFILL MATERIAL
A method of dispensing an underfill material on a semiconductor device package. A substrate having a semiconductor chip electrically connected thereto and offset from the substrate by solder joints is provided. The semiconductor chip has a footprint defined by a length and width of the semiconductor chip. Standoff heights between the substrate and the semiconductor chip are calculated and used to determine a volume of underfill material needed to substantially fill a space between the substrate and the semiconductor chip. The determined volume of underfill material is dispensed on the substrate such that the space between the substrate and the semiconductor chip is substantially filled by the underfill material. The method may allow for improved dispensing an underfill material to substantially fill the space between the substrate and semiconductor chip when variations in standoff height are present.
Semiconductor device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.
Underfill film for semiconductor package and method for manufacturing semiconductor package using the same
An underfill film for semiconductor packages and a method for manufacturing a semiconductor package using the underfill film are disclosed. The underfill film includes an adhesive layer in which a melt viscosity and an onset temperature are adjusted to a predetermined range such that production efficiency may be improved by simplifying packaging process of the semiconductor packages. Also the underfill film and the manufacturing process may improve connection reliability of the package.