Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.

Embodiments include forming an interposer having reinforcing structures disposed in a core layer of the interposer. The interposer may be attached to a package device by electrical connectors. The reinforcing structures provide rigidity and thermal dissipation for the package device. Some embodiments may include an interposer with an opening in an upper core layer of the interposer to a recessed bond pad. Some embodiments may also use connectors between the interposer and the package device where a solder material connected to the interposer surrounds a metal pillar connected to the package device.

A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.

A connection arrangement for forming a component carrier structure is disclosed. The connection arrangement includes a first electrically conductive connection element and a second electrically conductive connection element. The first connection element and the second connection element are configured such that, upon connecting the first connection element with the second connection element along a connection direction, a form fit is established between the first connection element and the second connection element that limits a relative motion between the first connection element and the second connection element in a plane perpendicular to the connection direction. A component carrier and a method of forming a component carrier structure are also disclosed.

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.

Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.

Disclosed are a driving backplane and a display apparatus, including: a base substrate, a first conducting layer disposed on one side of the base substrate, a second conducting layer disposed on one side, facing away from the base substrate, of the first conducting layer, and a first insulating layer disposed between the first conducting layer and the second conducting layer, where the second conducting layer includes a plurality of pads, and each pad is connected with the first conducting layer through at least two first via holes.

A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

An electronic component module according to an embodiment includes a substrate, an electronic component, and a connection device. The substrate includes an electrode array. The electronic component includes an electrode array. The connection device that includes a plurality of post parts including respective conductive parts and a base for supporting the plurality of post parts. The connection device is interposed between the substrate and the electronic component, and is configured in a manner that the conductive parts electrically connect the electrode array of the substrate and the electrode array of the electronic component to each other via solder.