A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor.

A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.

An electronic device includes: a first resin layer having a first resin layer main surface and a first resin layer inner surface; a columnar conductor having a columnar conductor main surface and a columnar conductor inner surface and penetrating the first resin layer in direction z; a wiring layer connecting the first resin layer main surface and the first conductor main surface; an electronic component being electrically connected and joined to the wiring layer; a second resin layer having a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface, covering the wiring layer and the electronic component; and an external electrode closer to the side where the first resin layer inner surface faces than the first resin layer and is electrically connected to the columnar conductor.

A micro LED display manufacturing method according to various embodiments may include: a first operation of bonding an anisotropic conductive film including a plurality of conductive particles onto one surface of a prepared substrate, the one surface including a circuit part; a second operation of forming a bonding layer on the anisotropic conductive film; a third operation of positioning a plurality of micro LED chips above the bonding layer, the micro LED chips being arranged on a carrier substrate while being spaced a first distance apart from the substrate; a fourth operation of attaching the plurality of micro LED chips onto the bonding layer by means of laser transfer; and a fifth operation of forming a conductive structure for electrically connecting a connection pad to the circuit part through the conductive particles by means of heating and pressurizing.

There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.

A semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device. The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant. The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

Methods for reducing heat transfer in semiconductor devices, and associated systems and devices, are described herein. In some embodiments, a method of manufacturing a semiconductor device includes forming a channel in a region of a substrate between a first die stack and a second die stack. The first die stack includes a plurality of first dies attached to each other by first film layers and the second die stack includes a plurality of second dies attached to each other by second film layers. The channel extends entirely through a thickness of the substrate. The method also includes applying heat to the first die stack to cure the first film layers. The channel reduces heat transfer from the first die stack to the second die stack.

Provided are an underfill material capable of realizing low-pressure mounting and voidless mounting, and a method for manufacturing a semiconductor device using the same. The underfill material includes a main composition containing an acrylic polymer, an acrylic monomer, and a maleimide compound, and the acrylic polymer is contained in a range of 10 parts by mass or more and 60 parts by mass or less in 100 parts by mass of the main composition, and the maleimide compound is contained in a range of 20 parts by mass or more and 70 parts by mass or less in 100 parts by mass of the main composition. Low-pressure mounting and the voidless mounting can be realized.

Provided are an underfill material capable of realizing low-pressure mounting and voidless mounting, and a method for manufacturing a semiconductor device using the same. The underfill material includes a main composition containing an acrylic polymer, an acrylic monomer, and a maleimide compound, and the acrylic polymer is contained in a range of 10 parts by mass or more and 60 parts by mass or less in 100 parts by mass of the main composition, and the maleimide compound is contained in a range of 20 parts by mass or more and 70 parts by mass or less in 100 parts by mass of the main composition. Low-pressure mounting and the voidless mounting can be realized.