A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

The present invention discloses a transferring method, a manufacturing method, a device and an electronics apparatus of micro-LED. The method for transferring micro-LED at wafer level comprises: temporarily bonding micro-LEDs on a laser-transparent original substrate onto a carrier substrate via a first bonding layer; irradiating the original substrate with laser, to lift-off selected micro-LEDs; performing a partial release on the first bonding layer, to transfer the selected micro-LEDs to the carrier substrate; temporarily bonding the micro-LEDs on the carrier substrate onto a transfer head substrate via a second bonding layer; performing a full release on the first bonding layer, to transfer the micro-LEDs to the transfer head substrate; bonding the micro-LEDs on the transfer head substrate onto a receiving substrate; and removing the transfer head substrate by releasing the second bonding layer, to transfer the micro-LEDs to the receiving substrate.

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.

There is a need to improve reliability of the semiconductor device.

A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h.sub.1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h.sub.2 of the solder layer is measured from the upper surface of the resist layer. Thickness h.sub.1 is greater than or equal to a half of thickness h.sub.2 and is smaller than or equal to thickness h.sub.2.

There is a need to improve reliability of the semiconductor device.

A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h.sub.1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h.sub.2 of the solder layer is measured from the upper surface of the resist layer. Thickness h.sub.1 is greater than or equal to a half of thickness h.sub.2 and is smaller than or equal to thickness h.sub.2.

A solder bump formed on an Ni electrode with the use of a solder ball containing Bi as a main component and Sn as a sub component. The solder ball contains Sn from 1.0 to 10.0 mass % and at most 1.0 mass % of at least one of Cu and Ag. A solder joint portion obtained by use of the solder bump has at least one of Sn and an SnBi eutectic alloy.