The invention discloses a light engine array comprises a multiple light engines arranged into an array, multiple dams located on a first surface of the light engines; and the dams combined a dam array.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces, the surfaces: being separated by a non-zero distance shorter than 10 micrometers; having an area greater than 100 mm.sup.2; being connected by an assembly of electrical interconnection elements spaced apart from one another by a space void of matter. This method includes applying a deposit of thin atomic layers onto the device to form a layer of mineral material covering at least the interconnection elements, the layer of mineral material having a permeability to water vapor smaller than or equal to 10.sup.−3 g/m.sup.2/day.

A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer.

A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer.

A method for manufacturing a semiconductor device includes: providing a support with a semiconductor light-emitting element including a first electrode and a second electrode; providing a base including a first interconnect terminal and a second interconnect terminal; forming a first metal layer on the support to cover the first and the second electrodes; forming a second metal layer on the base to cover the first and the second interconnect terminals; arranging the first and second electrodes and the first and second interconnect terminals to respectively face each other, and providing electrical connection therebetween by atomic diffusion; and rendering electrically insulative or removing portions of the first metal layer and the second metal layer that are outside thereof defined between the first and second electrodes and the first and second interconnect terminals.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.