Provided herein is a solder paste having low viscosity and easy coatability, and that provides high reinforcement for electronic components while satisfying both high room-temperature adhesion and high repairability, and forming a cured product of excellent properties, for example, high insulation against humidity. Amount structure including an electronic component mounted with the solder paste is also provided. The solder paste contains a solder powder and a flux. The flux contains an epoxy resin, a reactive diluent, a curing agent, an organic acid, and a rubber modified epoxy resin. The reactive diluent contains a compound having two or more epoxy groups, and has a viscosity of 150 mPa.Math.s or more and 700 mPa.Math.s or less. The reactive diluent has a total chlorine content of 0.5 weight % or less, and is contained in a proportion of 5 weight % or more and 45 weight % or less with respect to a total weight of the flux.

In an embodiment, an interconnection structure includes a first semiconductor device including a conductive stud, a second device including a contact pad, an adhesive layer including an organic component arranged between a distal end of the conductive stud and the contact pad, the adhesive layer coupling the conductive stud to the contact pad, and a conductive layer extending from the conductive stud to the contact pad. The conductive layer has a melting point of at least 600 C.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.

An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.

An electronic device includes: an electronic component including an external connection terminal; and a lead frame (metal member) connected to the external connection terminal. The lead frame is disposed with a pad. The pad overlaps the external connection terminal in plan view, and at least a portion of the pad is located outside the external shape of the electronic component in plan view. The pad and the external connection terminal are connected by means of a conductive bonding member. The pad and the electronic component are bonded together with a resin. The resin extends to a region of the pad located outside the external shape of the electronic component in plan view.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

The invention discloses a light engine array having at least an anode and a cathode comprising: a first type semiconductor layer; an active layer; and a second type semiconductor layer; a cathode electrode has a conductive metal layer in electrical contact with a portion of the first type semiconductor layer, and the second type semiconductor layer to form a short circuit structure in a common cathode region; and an anode electrode has the conductive metal layer and coupled to a portion of the first type semiconductor layer; wherein, the anode electrode is electrically isolated with the active layer and the second type semiconductor layer in a sub-pixel region.