A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.

A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.

A display apparatus is provided. The display apparatus includes a display substrate and a plurality of pads arranged above the display substrate. Each of the plurality of pads includes a first conductive layer, at least a portion of which is covered by an insulating film, a second conductive layer arranged above the first conductive layer, and a clamping portion formed in the second conductive layer.

In a method of manufacturing an electronic device, a solder paste is coated on a substrate pad of a substrate. An electronic product is disposed on the substrate such that a solder on an input/output pad of the electronic product makes contact with the solder paste. A first microwave is generated toward the solder paste during a reflow stage to heat the solder paste. A phase of the first microwave is changed during the reflow stage. Heating of the solder paste causes the solder to reflow, thereby forming a solder bump between the substrate pad and the input/output pad.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

Achieving homogeneous and heterogeneous integration for 2.5D and 3D integrated circuit, chip-to-wafer, chip-to-substrate, or wafer-to-wafer bonding is an essential technology. The landing wafer or substrate is bonded with a carrier by using a temporary bonding material before thinning the landing wafer to the desired thickness. Upon completion of redistribution layer formation, Cu pad formation, or other backside processing, dies or wafers with through-silicon vias are stacked onto the landing substrate before molding and singulation. As the landing wafer usually has interconnection metals in the bond line, and those interconnection metals are typically made from lead-free solder alloys, deformation of those solder alloys during thermocompression bonding becomes an issue for manufacturers. To address this issue, a polymeric material with desired strengths is coated on the device wafer to form a conformal protective layer on top of solder alloys, thus enabling temporary bonding and debonding processes.

A module includes a substrate, a plurality of components on an upper surface of the substrate, a component on a lower surface of the substrate, solder balls on the lower surface, sealing resin layers stacked on the upper surface and the lower surface of the substrate, and a shield film covering a side surface and an upper surface of the module. Part of each solder ball is exposed from a surface of the sealing resin layer, and the exposed parts are shaped to protrude from the sealing resin layer. The module can be connected to a mother substrate by connecting the protruding parts of the solder balls. There are gaps between the solder balls and the sealing resin layer, and the occurrence of cracks in the solder balls can be suppressed by reducing stress arising from a difference in thermal expansion coefficient between the solder and the resin.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 μm.