A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.

A method for fabricating a three-dimensional (3D) electronic device. A liquid support material (e.g., an epoxy acrylate with a photoinitiator) is applied by a laser-induced forward transfer (LIFT) process to a printed circuit board (PCB) having one or more connectors and one or more electronic components thereon, and then cured to solid form by cooling and/or exposure to ultraviolet (UV) radiation. A layer of conductive material (e.g., a metal) is printed on the solidified support material by LIFT to electrically connect the one or more electronic components to respective ones of the connectors on the PCB. Subsequently, the layer of conductive material is dried by heating and metal particles in the conductive layer sintered using a laser beam. The assembly may then be encapsulated in an encapsulant.

Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.

Disclosed in one example is an apparatus including a substrate, a sensor over the substrate including an active surface and a sensor bond pad, a molding layer over the substrate and covering sides of the sensor, the molding layer having a molding height relative to a top surface of the substrate that is greater than a height of the active surface of the sensor relative to the top surface of the substrate, and a lidding layer over the molding layer and over the active surface. The lidding layer and the molding layer form a space over the active surface of the sensor that defines a flow channel.

A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes; (2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.

The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 m and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.