In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.

An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.

A fan-out package structure is disclosed. The fan-out package structure includes an antenna main body; a redistribution layer (RDL); and an antenna auxiliary body in the RDL. An antenna system is also disclosed. The antenna system includes: an antenna main body, arranged to provide a first resonance; and an antenna auxiliary body, arranged to provide a second resonance through parasitic coupling to the antenna main body; wherein a dimension of the antenna main body is greater than a dimension of the antenna auxiliary body. An associated semiconductor packaging method is also disclosed.

A fan-out package structure is disclosed. The fan-out package structure includes an antenna main body; a redistribution layer (RDL); and an antenna auxiliary body in the RDL. An antenna system is also disclosed. The antenna system includes: an antenna main body, arranged to provide a first resonance; and an antenna auxiliary body, arranged to provide a second resonance through parasitic coupling to the antenna main body; wherein a dimension of the antenna main body is greater than a dimension of the antenna auxiliary body. An associated semiconductor packaging method is also disclosed.