A semiconductor device of the present invention includes a first main electrode and a second main electrode respectively disposed on a first main surface and a second main surface of a semiconductor substrate, a protective film disposed on an edge part of the first main electrode; and a first metal film disposed in a region enclosed by the protective film on the first main electrode. The first metal film has a film thickness at a central portion larger than that at a part in contact with the protective film, and has irregularities on a surface thereof.

An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.

A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.

A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.

A semiconductor package includes a carrier having a recess, a semiconductor die arranged on the carrier such that a first side of the semiconductor die faces the carrier, and a contact clip arranged over a second side of the semiconductor die, opposite the first side. The contact clip includes a lowered part. The lowered part is arranged in the recess.

The present disclosure describes a power module having a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies. The substrate has a top surface with a first trace and a second trace. The first plurality of vertical power devices and the second plurality of vertical power devices are electrically coupled to form part of a power circuit. The first plurality of vertical power devices is electrically and mechanically directly coupled between the first trace and a bottom of a first elongated bar of the first terminal assembly. The second plurality of vertical power devices are electrically and mechanically directly coupled between the second trace and a bottom of a second elongated bar of the second terminal assembly.

A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.

A low parasitic inductance power module, which includes an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal includes a positive power terminal and a negative power terminal, the top metal insulating substrate and the bottom metal insulating substrate are stacked, chips are sintered on faces of both the top metal insulating substrate and the bottom metal insulating substrate opposite to each other, and the positive power terminal, the negative power terminal, and the output power terminal are all electrically connected with the chips; and the output power terminal includes a welding portion and a connecting portion located outside the plastic package shell, and the welding portion is located between the top metal insulating substrate and the bottom metal insulating substrate.

Various embodiments may provide a semiconductor package. The semiconductor package may include a first electrical component, a second electrical component, a first heat sink, and a second heat sink bonded to a first package interconnection component and a second package interconnection component. The first package interconnection component and the second package interconnection component may provide lateral and vertical interconnections in the package.

An electrical connection member (1, 301, 401, 501, 601) includes a clad material (10, 110, 610) including at least both a first Cu layer (12) made of a Cu material and a low thermal expansion layer (11) made of an Fe material or Ni material having an average thermal expansion coefficient from room temperature to 300° C. smaller than that of the first Cu layer, the first Cu layer and the low thermal expansion layer being bonded to each other.