A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.

A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.

A method for forming a ball bond for an integrated circuit formed on a semiconductor die includes forming a ball at a first send of a conductive wire inserted in a capillary tool and lowering the capillary tool toward a pad on the semiconductor die positioned on a support surface. The method further includes moving, using a motor, the support surface relative to the capillary tool to thereby bond the ball, without using ultrasound, to the pad and then raising the capillary tool.

A method for forming a ball bond for an integrated circuit formed on a semiconductor die includes forming a ball at a first send of a conductive wire inserted in a capillary tool and lowering the capillary tool toward a pad on the semiconductor die positioned on a support surface. The method further includes moving, using a motor, the support surface relative to the capillary tool to thereby bond the ball, without using ultrasound, to the pad and then raising the capillary tool.

One aspect relates to a method that includes bonding an electrically conductive element to a bonding surface of a bonding partner by increasing a temperature of a bonding section of the electrically conductive element from an initial temperature to an increased temperature by passing an electric heating current through the bonding section, and pressing the bonding section with a pressing force against the bonding surface using a sonotrode and introducing an ultrasonic vibration into the bonding section via the sonotrode such that the increased temperature of the bonding section, the ultrasonic signal in the bonding section and the pressing force are simultaneously present and cause the formation of a tight and direct bond between the bonding section and the bonding surface.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

Method for manufacturing a semiconductor device includes: preparing a first subassembly in which an upper surface of the conductive spacer is soldered on the second conductive member and preliminary solder is provided on a lower surface of the conductive spacer; preparing a second subassembly in which the lower surface of the semiconductor element is soldered on the first conductive member and the bonding wire is joined on upper surface of the semiconductor element; and soldering the upper surface of the semiconductor element in the second subassembly on the lower surface of the conducive spacer in the first subassembly by melting the preliminary solder in the first subassembly

An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.