A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure.

A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including -alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.

A versatile, thermally stable and economically effective corrosion inhibition treatment for copper (Cu) metal and selected metals surface through a single step chemical vapor deposition (CVD) of selected inhibitor compounds at temperatures as low as 100-200 C. is described in this invention. The resulting CVD deposited inhibition coating is thermally stable to 300 C. and protects Cu and selected metals from active corrosion in various technologically important operational environments. The selective coating for copper metal is achieved by controlling the chemistry of bonding between the Copper metal surface and inhibitor material used. The technique can be accomplished by using one or more inhibitors separately or in combination in order to create an all-terrain stable & robust corrosion prevention coating for copper metal.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

A semiconductor device is provided that can minimize the occurrence of poor joining between a copper electrode and a copper wire. The semiconductor device includes a semiconductor substrate; a copper electrode layer formed on the semiconductor substrate; a metallic thin-film layer formed on the copper electrode layer for preventing oxidation of the copper electrode layer, the metallic thin-film layer having an opening through which the copper electrode layer is exposed, the opening being located on an inner side relative to an outer periphery of the metallic thin-film layer; and an interconnection member containing copper as a main component, the interconnection member including a joining region covering the opening, the interconnection member being joined to the metallic thin-film layer and joined to the copper electrode layer in the opening.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

The reliability of semiconductor device is improved. The method of manufacturing a semiconductor device has a step of performing plasma treatment prior to the wire bonding step, and the surface roughness of the pads after the plasma treatment step is equal to or less than 3.3 nm.

A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure.

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.