Patent classifications
H01L2224/85385
SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT
A substrate for mounting a semiconductor element thereon includes a metal plate and columnar terminal portions composed only of plating layers and formed on one-side surface of the metal plate. The columnar terminal portions include, as an outermost plating layer, a roughened silver plating layer having acicular projections. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer, which are to serve as terminals and the like, to be thin.
DEVICE FOR MOUNTING SEMICONDUCTOR ELEMENT, LEAD FRAME, AND SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT
A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.
SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT
A substrate for mounting a semiconductor element thereon has columnar terminal portions formed by concavities provided on an upper surface of a metal plate made of a copper-based material, and is provided with a roughened silver plating layer having acicular projections, applied, as the outermost plating layer, to top faces of the columnar terminal portions. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon facilitates thin design of semiconductor packages produced by flip-chip mounting, can be manufactured with improved productivity owing to reduction in cost and operation time, achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
LEAD FRAME
A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering only top faces on the upper surface side of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
LEAD FRAME
A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering the entire surface of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
LEAD FRAME
A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering top faces and faces that form concavities or a through hole between the top faces and bottom faces of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
Substrate for mounting semiconductor element
A substrate for mounting a semiconductor element thereon includes a metal plate and columnar terminal portions composed only of plating layers and formed on one-side surface of the metal plate. The columnar terminal portions include, as an outermost plating layer, a roughened silver plating layer having acicular projections. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer, which are to serve as terminals and the like, to be thin.
Conductive trace design for smart card
A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.
Lead frame
A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering the entire surface of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
CONDUCTIVE TRACE DESIGN FOR SMART CARD
A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.