In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

A wiring substrate includes a first wiring layer, a first insulation layer, and a second wiring layer. The first insulation layer covers an upper surface and a side surface of the first wiring layer and exposes a lower surface of the first wiring layer. The second wiring layer is stacked on at least one of a lower surface of the first insulation layer and the lower surface of the first wiring layer.

A wiring substrate includes a first wiring layer, a first insulation layer, and a second wiring layer. The first insulation layer covers an upper surface and a side surface of the first wiring layer and exposes a lower surface of the first wiring layer. The second wiring layer is stacked on at least one of a lower surface of the first insulation layer and the lower surface of the first wiring layer.

A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

A semiconductor power package includes a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing. The semiconductor power package further includes a power semiconductor chip bonded on the electrically conducting chip carrier. A covering material is provided to embed the power semiconductor chip. The covering material has an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.