Patent classifications
H01L2224/85801
ELECTRONIC DEVICE WITH THREE DIMENSIONAL THERMAL PAD
An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
ELECTRONIC DEVICE WITH THREE DIMENSIONAL THERMAL PAD
An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
SEMICONDUCTOR PACKAGE WITH A CAVITY IN A DIE PAD FOR REDUCING VOIDS IN THE SOLDER
A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.
SEMICONDUCTOR PACKAGE WITH A CAVITY IN A DIE PAD FOR REDUCING VOIDS IN THE SOLDER
A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.
Solder ball, solder joint, and joining method
A solder ball includes 0.1% by mass or more and 10% by mass or less of In and a remainder of Sn. The ball has a yellowness (b*) in an L*a*b* color system of 2.8 or more and 15.0 or less and a lightness (L*) of 60 or more and 100 or less. The ball further includes at least one element selected from a group of 0% by mass or more and 4% by mass or less of Ag, 0% by mass or more and 1.0% by mass or less of Cu, 0% to 3% by mass in total of Bi and/or Sb, and 0% to 0.1% by mass in total of an element selected from a group of Ni, Co, Fe, Ge, and P, excluding a solder ball including 3% by mass of Ag, 0.5% by mass of Cu, 0.2% by mass of In and a remainder of Sn.
Semiconducter device with filler to suppress generation of air bubbles and electric power converter
A semiconductor device including: an insulating substrate having a conductor layer on the upper face and the lower face and a semiconductor element mounted on the upper conductor layer; a base plate bonded to the lower conductor layer; a case member surrounding the insulating substrate and bonded to the surface of the base plate to which the conductor layer bonded to the lower face; a first filler being a silicone composition filled in a region surrounded by the base plate and the case member; and a second filler being injected into a region below the first filler and surrounding a peripheral edge portion of the insulating substrate, whose height from the base plate is higher than the upper face and is lower than a bonding face between the semiconductor element and the upper conductor layer.
SOLAR CELL MODULE INCLUDING SOLAR CELLS
The finger electrode is formed by hard-soldered silver paste. The melting point of the first type solder layer provided on the surface of the terminal wiring member is higher than the melting point of the second type solder layer provided on the surface of the wire. The first width, in the first direction, of the second type solder layer in the first portion where the wire is connected to the terminal wiring member is larger than the second width, in the first direction, of the second type solder layer in the second portion where the wire is connected to the finger electrode.
Abstracted NAND Logic In Stacks
A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.
METHOD AND DEVICE FOR ESTABLISHING A WIRE CONNECTION AS WELL AS A COMPONENT ARRANGEMENT HAVING A WIRE CONNECTION
A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.
Methods for connecting inter-layer conductors and components in 3D structures
Systems and methods for creating interlayer mechanical or electrical attachments or connections using filaments within a three-dimensional structure, structural component, or structural electronic, electromagnetic, or electromechanical component/device.