An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

A semiconductor package may include: a substrate; a first sub-semiconductor package disposed over the substrate, the first sub-semiconductor package including a first buffer chip and a first memory chip; and a second memory chip disposed over the first sub-semiconductor package, wherein the first buffer chip and the first memory chip are connected to each other using a first redistribution line, and wherein the first buffer chip and the second memory chip are connected to each other using a second bonding wire.

A semiconductor package includes a substrate including an upper pad at a top surface of the substrate, a semiconductor chip on the substrate and including a chip pad at a top surface of the semiconductor chip, a connecting structure on the semiconductor chip and including a connecting pad at a top surface of the connecting structure and electrically connected to the upper pad, an encapsulant covering the substrate, the semiconductor chip, and the connecting structure, and a test terminal on the connecting structure and extending through the encapsulant. The connecting structure electrically interconnects the semiconductor chip and the test terminal.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad.

A semiconductor package including a first lower stack on a substrate and including first lower semiconductor chips, a redistribution substrate on the first lower stack, a redistribution connector electrically connecting the substrate to the redistribution substrate, a first upper stack on the redistribution substrate and including first upper semiconductor chips, a first upper connector electrically connecting the redistribution substrate to the first upper stack, a second upper stack horizontally spaced apart from the first upper stack and including second upper semiconductor chips, and a second upper connector electrically connecting the redistribution substrate to the second upper stack may be provided. The redistribution connector may be on one side of the redistribution substrate. The first upper connector may be on one side of the first upper stack. The second upper connector may be on one side of the second upper stack.

A semiconductor package includes first semiconductor chips stacked on a package substrate, a lowermost first semiconductor chip of the first semiconductor chips including a recessed region, and a second semiconductor chip inserted in the recessed region, the second semiconductor chip being connected to the package substrate.

Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

A light emitting device includes: a substrate; a package having an upward-facing surface and an inward-facing surface that define a recess; a light emitting element mounted on the upward-facing surface of the package; a first cover member including: a light transmitting layer that contacts at least a portion of a lateral surface of the light emitting element, the light transmitting layer having an upper surface that is inclined from the lateral surface of the light emitting element towards the upward-facing surface of the package, and a reflecting material-containing layer located below the light-transmitting layer; and a second cover member that contacts the inward-facing surface of the package and is separated from the light emitting element.