According to one embodiment, in a semiconductor manufacturing apparatus, a controller relatively moves a bonding tool and a stage close to each other while causing a semiconductor chip to adhere by suction to a surface via a tape using at least a first suction structure in a first period. In a second period, the controller controls the temperature of the bonding tool to a first target temperature while keeping substantially equal to a target pressure a pressure applied to the semiconductor chip by the bonding tool. In a third period, the controller controls a relative distance between the bonding tool and the stage so that the pressure applied to the semiconductor chip by the bonding tool is kept equal to the target pressure and controls the temperature of the bonding tool to a second target temperature. The second target temperature is higher than the first target temperature.

According to one embodiment, in a semiconductor manufacturing apparatus, a controller relatively moves a bonding tool and a stage close to each other while causing a semiconductor chip to adhere by suction to a surface via a tape using at least a first suction structure in a first period. In a second period, the controller controls the temperature of the bonding tool to a first target temperature while keeping substantially equal to a target pressure a pressure applied to the semiconductor chip by the bonding tool. In a third period, the controller controls a relative distance between the bonding tool and the stage so that the pressure applied to the semiconductor chip by the bonding tool is kept equal to the target pressure and controls the temperature of the bonding tool to a second target temperature. The second target temperature is higher than the first target temperature.

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.

A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.

A bonding apparatus includes an ultrasonic oscillator which generates ultrasonic vibration, a stage disposed under the ultrasonic oscillator, and an embossed sheet disposed between the ultrasonic oscillator and the stage. The embossed sheet includes a body and a plurality of protrusions protruding downward from a lower surface of the body which faces the stage.

A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

The present application discloses a semiconductor device with stacked dies and the method for fabricating the semiconductor device with the stacked dies. The semiconductor device includes a first semiconductor die including a first substrate including a first and a second region, a first circuit layer on the first substrate, a control circuit on the first region and in the first circuit layer; and through die vias along the first circuit layer and the second region; a second semiconductor die stacked on the first semiconductor die and including second conductive pads connected to the through die vias and the control circuit; and a third semiconductor die stacked under the first semiconductor die and including third conductive pads connected to the through die vias and the control circuit. The through die vias, the second conductive pads, and the third conductive pads configure transmission channels through which the control circuit is capable to access the second and the third semiconductor die.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.