A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.

Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

The present invention provides a bump structure of chip disposed on a surface of a chip and comprises a plurality of connecting-bump sets. Each connecting-bump set includes a first connecting hum and a second connecting hump. The first connecting bump and the second connecting bump include corresponding blocking structures. While disposing the chip on a board member, the blocking structure of the first connecting bump and the blocking structure of the second connecting bump block the conductive medium and retard the flow of the conductive medium. The conductive medium is forced to flow between the first connecting bump and the second connecting bump and thus preventing the conductive particles in the conductive medium from leaving the surfaces of the connecting bumps. In addition, there is a flow channel between the first and second connecting bumps. One or more width of the flow channel is between 0.1 μm and 8 μm.