Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. The fill layer is composed of noble metal (such as copper) and active metal (such as Zn). Then the fill metal layer is turned into a metal alloy after annealing. A dealloying is performed to the metal alloy to remove the active metal from the metal alloy while the noble metal remains to self-assemble into porous (nanoporous) structure metal. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using dielectric-to-dielectric direct bonding techniques, with the fill nanoporous metal layer in the recesses in one of the first and second interconnect structures. After the following batch annealing, the fill nanoporous metal layer turns into pure bulk metal same as conductive interconnect structures due to the heat expansion of conductive interconnect structures and nanoporous metal densification.

A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

This application is directed to a semiconductor system including a substrate, an electronic device, a plurality of compliant interconnects and a support structure. The substrate has a first surface and a plurality of first contacts formed on the first surface. The electronic device has a second surface facing the first surface of the substrate, and a plurality of second contacts formed on the second surface. The compliant interconnects are disposed between the first surface of the substrate and the second surface of the electronic device, and are configured to electrically couple the first contacts on the first surface of the substrate to the second contacts on the second surface of the electronic device. The support structure is coupled to the substrate and the electronic device, and extends beyond a footprint of the electronic device. The support structure is configured to mechanically couple the electronic device to the substrate.

A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.

In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.

A flat plate frame is formed, which is flat plate-shaped, which has an opening penetrating its front and rear surfaces and groove terminal patterns formed on its front surface, and which contains a semi-cured thermosetting resin. Then, an insulating substrate is disposed on the rear surface so as to cover the opening of the flat plate frame, external connection terminals are disposed on the terminal patterns, and heating is carried out. As a result, a terminal package to which the insulating substrate and external connection terminals are firmly joined is produced using the flat plate frame. The external connection terminals included in the terminal package are reliably and firmly joined to the terminal package. Therefore, the external connection terminals are not displaced when wires are bonded to the external connection terminals.

A flat plate frame is formed, which is flat plate-shaped, which has an opening penetrating its front and rear surfaces and groove terminal patterns formed on its front surface, and which contains a semi-cured thermosetting resin. Then, an insulating substrate is disposed on the rear surface so as to cover the opening of the flat plate frame, external connection terminals are disposed on the terminal patterns, and heating is carried out. As a result, a terminal package to which the insulating substrate and external connection terminals are firmly joined is produced using the flat plate frame. The external connection terminals included in the terminal package are reliably and firmly joined to the terminal package. Therefore, the external connection terminals are not displaced when wires are bonded to the external connection terminals.