Patent classifications
H01L2224/9222
Package and method of fabricating the same
Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.
Package and method of fabricating the same
Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.
PACKAGE STRUCTURE
A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
PACKAGE STRUCTURE
A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
Semiconductor package and method
In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
Semiconductor package and method
In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
COMPOSITE BRIDGE DIE-TO-DIE INTERCONNECTS FOR INTEGRATED-CIRCUIT PACKAGES
Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHOD OF FORMING THE SAME
Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.
THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHOD OF FORMING THE SAME
Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.
PACKAGE AND MANUFACTURING METHOD THEREOF
A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant. The second package structure is electrically connected to the redistribution structure through the conductive structures.