The embodiment of the present disclosure discloses a method of packaging a chip and a chip package structure. the method of packaging the chip includes: mounting at least one chip to be packaged and at least one electrically conductive module on a carrier, wherein the at least one chip to be packaged has a back surface facing upwards and an active surface facing towards the carrier, and the at least one electrically conductive module is in the vicinity of the at least one chip to be packaged; forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the at least one electrically conductive module; detaching the carrier to expose the active surface of the at least one chip to be packaged and a first surface of the at least one electrically conductive module; and completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged and the first surface of the at least one electrically conductive module. The present disclosure reduces the difficulty of packaging a chip by mounting the active surface of a chip to be packaged and an electrically conductive module on a carrier and thus saves the cost of packaging.

A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

A semiconductor package includes: a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer at least partially surrounding the first redistribution pattern; a first semiconductor chip disposed on the first redistribution structure; a first molding member at least partially surrounding the first semiconductor chip and the first redistribution structure; a conductive pillar passing through the first molding member; a second redistribution structure disposed on the first molding member and including a second redistribution pattern and a second redistribution insulating layer at least partially surrounding the second redistribution pattern; a second semiconductor chip disposed on the second redistribution structure; and a second molding member at least partially surrounding the second semiconductor chip and the second redistribution structure.

A semiconductor package is provided, comprising: a package substrate; a first plurality of semiconductor dice disposed on a front side of the package substrate; an embedded sub-package disposed on a back side of the package substrate, comprising: a sub-package substrate, wherein a front side of the sub-package substrate is attached to the back side of the package substrate; an interconnection layer attached to a back side of the sub-package substrate, comprising a second plurality of vertical interconnection portions and at least one horizontal interconnection portion; and a second plurality of semiconductor dice disposed on the back side of the sub-package substrate through the interconnection layer; and a first plurality of vertical interconnection portions disposed on the back side of the package substrate; and solder bumps attached to the first plurality of vertical interconnection portions.

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

A semiconductor package may include a first wiring structure including a plurality of first redistribution patterns and a plurality of first redistribution insulating layers, a second wiring structure on the first wiring structure and including a plurality of second redistribution patterns and a plurality of second redistribution insulating layers, a semiconductor chip between the first wiring structure and the second wiring structure, an expanded layer including a plurality of connection structures electrically connecting the first wiring structure and the second wiring structure to each other and an encapsulant surrounding the plurality of connection structures and the semiconductor chip, a ceramic shield layer between the expanded layer and the second wiring structure, and a plurality of via structures penetrating the ceramic shield layer and electrically connecting the plurality of connection structures and the plurality of second redistribution patterns to each other.

A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

A semiconductor package according to an embodiment includes a first semiconductor die including a back side bonding structure; and a second semiconductor die including a front side bonding structure bonded to the back side bonding structure, wherein the back side bonding structure includes a first dielectric layer; and first bonding pads passing through the first dielectric layer, the front side bonding structure includes a second dielectric layer bonded to the first dielectric layer; and second bonding pads with each second bonding pad bonded to a respective first bonding pad and passing through the second dielectric layer, and the first dielectric layer includes oblique edge portions around the first bonding pads at the surface facing the second dielectric layer.

A device includes a first die physically and electrically connected to a first set of redistribution layers, where the first set of redistribution layers include a first set of metal layers oriented along a first plane. The integrated device also includes a substrate and a second die disposed between the first set of redistribution layers and the substrate. The second die is physically and electrically connected to a second set of redistribution layers, where the second set of redistribution layers include a second set of metal layers oriented along a second plane. The second plane is non-parallel with respect to the first plane, and the second set of metal layers define conductive paths between various combinations of the substrate, the first die, and the second die.