A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

A method for manufacturing a semiconductor device is provided, including: preparing a first chip forming portion having a first semiconductor substrate, first metal pads provided at the substrate and a first circuit electrically connected to at least a part of the pads, and a second chip forming portion having a second semiconductor substrate, second metal pads provided at substrate and a second circuit electrically connected to at least a part of the pads; bonding the first and the second chip forming portions while joining the first and the second pads to form a bonding substrate having a non-bonded region between the first and the second chip forming portions at an outer peripheral portion thereof; and filling an insulating film into the non-bonded region, at least a part of the insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

A semiconductor device according to an embodiment includes: a bonding substrate which includes a first chip forming portion having first metal pads provided at a semiconductor substrate and a first circuit connected to the first metal pads, and a second chip forming portion having second metal pads joined to the first metal pads and a second circuit connected to the second metal pads and being bonded to the first chip forming portion; and an insulating film which is filled into a non-bonded region between the first chip forming portion and the second chip forming portion at an outer peripheral portion of the bonding substrate. At least a part of the insulating film contains at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

The present disclosure relates to a display substrate and a method for manufacturing the same. The display substrate includes: a substrate; a first electrode located on the substrate; and a conductive convex located on the first electrode. A dimension of a cross section of the conductive convex along a plane parallel to the substrate is negatively correlated to a distance from the cross section to a surface of the first electrode.

A package structure including an organic interposer substrate, a semiconductor die, conductive bumps, an underfill, and an insulating encapsulation is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the underfill encapsulates the conductive bumps and is in contact with the chamfered edges of the at least one semiconductor die. The insulating encapsulation covers the organic interposer substrate and laterally encapsulates the least one semiconductor die and the underfill.

A manufacturing method of a semiconductor structure includes at least the following steps. An encapsulated semiconductor die is disposed on a first surface of a circuit carrier to be in electrical contact with the circuit carrier. A second surface of the circuit carrier and an edge of the circuit carrier is protected with a patterned dielectric layer, where the second surface of the circuit carrier is opposite to the first surface, and the edge of the circuit carrier is connected to the second surface. A conductive terminal is formed to penetrate through the patterned dielectric layer to be in electrical contact with the circuit carrier.

A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of a portion of a sidewall of the photonic die, wherein a surface roughness of the edge coupling facet is less than a surface roughness of a sidewall of the insulating layer or a surface roughness of another portion of the sidewall of the photonic die.