A semiconductor package includes a base substrate, an insulating layer including a first region disposed on the base substrate and in which first and second openings are disposed and a second region, a remaining region of the base substrate other than the first region, a first semiconductor chip disposed on the base substrate and including bonding pads disposed closely to a first edge, at least one second semiconductor chip stacked on the first semiconductor chip in the form of a staircase toward a second edge, parallel to the first edge, and a molding portion covering the base substrate to encapsulate the first and second semiconductor chips, wherein the length of the first edge is disposed to overlap the second region, both ends of the second edge are disposed to overlap the first and second openings, and the molding portion fills the first and second openings.

A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, at least one light-emitting element extending in a direction, disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, and an insulating pattern layer disposed on the first electrode and the second electrode, the insulating pattern layer including a fixer disposed on at least part of the at least one light-emitting element, and a barrier surrounding the at least one light-emitting element.

A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

In a manufacturing method of a semiconductor device including a substrate having a front surface and a rear surface, and a film attached to the rear surface, the film is attached on the rear surface, a rear surface side groove is provided by half-cutting the substrate from the rear surface together with the film, a protective member is attached to the film after the rear surface side groove is provided, and a front surface side groove connected to the rear surface side groove is provided by dicing the substrate from the front surface after the protective member is attached.

A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

A method for self-assembling microelectronic components includes providing a self-aligning substrate having protrusions, each having a thickness greater than 1 μm and an upper face and flanks, the upper face and the flanks being hydrophobic. The method also includes providing dies, each die having a first face and a second hydrophilic face, and providing a self-assembling substrate. Finally, the method includes obtaining, by capillary effect, the self-alignment of each die through the first face thereof on a protrusion of the self-aligning substrate, then obtaining the assembly of the dies through the second hydrophilic face thereof on the self-assembling substrate by direct adhesion. Such a method has application in the industrial production of 3D integrated circuits.

A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.