A method includes providing first and second wafers; forming a first device layer in a top portion of the first wafer; forming a second device layer in a top portion of the second wafer; forming a first groove in the first device layer; forming a second groove in the second device layer; bonding the first and second wafers together after at least one of the first and second grooves is formed; and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

A light emitting diode apparatus includes a substrate, a first conductive type semiconductor layer, a second conductive type semiconductor layer, a mesa, a lower insulating layer, a first pad and a second pad. The substrate has a first surface and a second surface opposite to the first surface. The first conductivity type semiconductor layer is disposed on the first surface of the substrate. The mesa is disposed on the first conductive semiconductor layer and has an active layer and the second conductive semiconductor layer. A peripheral edge of the first conductive semiconductor layer is exposed. The lower insulating layer covers the mesa and the first conductive semiconductor layer and has a plurality of first openings exposing the first conductive semiconductor layer along a peripheral edge of the substrate.

The present invention addresses the problem of enlarging a sensing area in an ultrasonic probe so as to achieve a higher definition. This ultrasonic diagnostic equipment is provided with an ultrasonic probe that comprises: a CMUT chip (2a) that has drive electrodes (3e)-(3j), etc., arranged in a grid-like configuration on a rectangular CMUT element section (21); and a CMUT chip (2b) that has drive electrodes (3p)-(3u), etc., arranged in a grid-like configuration on the rectangular CMUT element section (21), that is adjacent to the CMUT chip (2a), and in which the drive electrodes (3e)-(3j) of the adjacent CMUT chip (2a) are electrically connected to the respective drive electrodes (3p)-(3u) via bonding wires (4f)-(4i), etc.

A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly. In another aspect, the emissive elements and fluidic assembly keys have differing vertical profiles useful in preventing detrapment.

Techniques are disclosed for forming a frame on the backplane comprising structures at least partially circumscribing or enclosing metal contacts on the backplane. In some embodiments, the frame may comprise a photoresist. The dimensions and structural integrity of the frame can help prevent misalignment and/or damage of physical obtrusions of light-emitting structures during a bonding process of the light-emitting structures to the backplane.

A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Electrolyte for a solid-state battery includes a body having grains of inorganic material sintered to one another, where the grains include lithium. The body is thin, has little porosity by volume, and has high ionic conductivity.

A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.