A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

A package structure and a manufacturing thereof are provided. The package structure includes a base, a chip, a control element and an underfill. The chip is disposed on the base and includes a recess, and the recess has a bottom surface and a sidewall. The control element is disposed between the base and the chip and disposed on the bottom surface of the recess, and a gap exists between the control element and the sidewall of the recess. The underfill is disposed in the recess. The chip and the control element are electrically connected to the base respectively.

In one example, an electronic device includes a semiconductor sensor device having a cavity extending partially inward from one surface to provide a diaphragm adjacent an opposite surface. A barrier is disposed adjacent to the one surface and extends across the cavity, the barrier has membrane with a barrier body and first barrier strands bounded by the barrier body to define first through-holes. The electronic device further comprises one or more of a protrusion pattern disposed adjacent to the barrier structure, which can include a plurality of protrusion portions separated by a plurality of recess portions; one or more conformal membrane layers disposed over the first barrier strands; or second barrier strands disposed on and at least partially overlapping the first barrier strands. The second barrier strands define second through-holes laterally offset from the first through-holes. Other examples and related methods are also disclosed herein.

A chip package includes a substrate, a first die, a second die, and a beam structure. The first die and the second die are disposed on a side of the substrate and are electrically connected to the substrate. The beam structure is disposed between the first die and the second die. A first end of the beam structure is stacked with and fixedly connected to a part of the first die, a second end is stacked with and fixedly connected to a part of the second die, and the beam structure is insulated from and connected to the first die and the second die. A thermal expansion coefficient of the beam structure is less than a thermal expansion coefficient of the substrate.

A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.

An electronic component module includes a substrate, an electronic component, an insulating resin, and a shield film. The insulating resin covers a first main surface side of the substrate. The insulating resin exposes an opposite surface of the electronic component. The shield film covers the insulating resin and the opposite surface of the electronic component. The opposite surface has an uneven portion. A concave portion of the uneven portion has a smoother shape than a convex portion of the uneven portion.

A silicon interposer may include an on-chip DC blocking capacitor, comprising: a first electrical connection to couple to a supply voltage and to cathodes of a plurality of photodiodes formed in a two-dimensional photodiode array on a first substrate, and a second electrical connection to couple to ground and to ground inputs of a plurality of transimpedance amplifiers on a second substrate; wherein the on-chip DC blocking capacitor is configured to be shared among a plurality of receiver circuits comprising the plurality of photodiodes and the plurality of transimpedance amplifiers; and wherein the silicon interposer comprises a substrate separate from the first substrate and the second substrate.

A semiconductor device according to the invention of the present application includes a support, a semiconductor chip provided on the support and a die bond material for bonding a back surface of the semiconductor chip to the support, wherein a plurality of cutouts is formed at edges formed between the back surface and side surfaces of the semiconductor chip connected to the back surface, and the die bond material is provided integrally over the plurality of cutouts.

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

In a semiconductor package in which a semiconductor substrate is mounted, thermal resistance of the semiconductor substrate is reduced. The semiconductor package includes a semiconductor substrate, an insulating layer, a metal layer, an interposer substrate, a mounting substrate, a signal transmission solder ball, and a solder member. A pad is provided on one surface of the semiconductor substrate. A different surface of the semiconductor substrate is covered with the insulating layer. The metal layer covers the insulating layer. A wire to be connected to the pad is formed on the interposer substrate. The signal transmission solder ball is jointed to the wire and the mounting substrate, and transmits a predetermined electrical signal. The solder member is jointed to the metal layer and the mounting substrate.