The present application relates to a chip heat dissipating structure, a chip structure, a circuit board and a supercomputing device, and the chip heat dissipating structure includes a metal layer, where the metal layer is covered on the chip. By adding a metal layer on the top of the chip, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip; the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, thus improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip.

A ball grid array device includes a monitoring circuit of inactive solder joints and a processor such as a field programmable gate array (FPGA) or other processor capable of determining the open or closed status of the monitoring circuit. The monitoring circuit traverses one or more of the solder joints between components being joined, such as a printed circuit board and an integrated circuit device. In certain embodiments, the inactive solder joints may be located within regions of the ball grid array that are predisposed to failure, such as at the periphery or corners of the printed circuit board, or proximate to regions that experience a broad range of operating temperatures. The failure of a solder joint within the monitoring circuit can be used to schedule maintenance of the ball grid array device prior to failure of an active solder joint.

A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.

A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.

A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

A micro-component comprises a component substrate having a first side and an opposing second side. Fenders project from the first and second sides of the component substrate and include first-side fenders extending from the first side and a second-side fender extending from the second side of the component substrate. At least two of the first-side fenders have a non-conductive surface and are disposed closer to a corner of the component substrate than to a center of the component substrate.

An electronic control device includes a substrate, a heat generating component mounted on the substrate, a heat dissipation unit thermally coupled to a surface of the heat generating component located on a side opposite to the substrate side, and a cooling mechanism thermally coupled to the heat dissipation unit. The heat dissipation unit includes a porous thermal conductor and a semi-cured resin which includes a heat conductive filler and is formed between at least the porous thermal conductor and the surface of the heat generating component.

A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.