Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.

Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.

A display device includes a display panel including a display area and a non-display area defined therein and including a plurality of signal pads overlapping the non-display area, an electronic component including a base layer with an upper surface and a lower surface, a plurality of driving pads disposed on the lower surface of the base layer, and a plurality of driving bumps respectively disposed on the plurality of driving pads, the plurality of driving bumps being respectively connected to the signal pads, and a filler disposed between the display panel and the electronic component. A first hole is defined in the upper surface of the base layer, and the first hole does not overlap the plurality of driving bumps in a plan view.

A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

The purpose of the invention is to counter measure a disconnection between the driver IC and the terminal when the terminal area of the electronic device is curved. One of the structures is as follows. An electronic device comprising: a driver IC installed in a terminal area, the terminal area being curved, wherein the driver IC has a circuit and plural bumps, the driver IC has a tapered portion formed on an opposite surface from a surface that the plural bumps are formed, the tapered portion overlaps with an outer most bump of the plural bumps.

A semiconductor device includes a substrate, first and second semiconductor chips, an adhesion layer, and a resin layer. The first and second semiconductor chips are provided on a surface of the substrate. The second semiconductor chip includes, on a side thereof facing the substrate, a first region and a second region that is recessed from the first region and is above at least part of the first semiconductor chip or at least part of a wire that electrically connects the first semiconductor chip and the substrate. The adhesion layer is provided at least between the first region of the second semiconductor chip and the substrate. The resin layer is on the surface of the substrate and enclosing the first and second semiconductor chips.

A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate to permit electroplating. In addition, the method may be used to directly connect a semiconductor die to the metal substrate of the package.

A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.