A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

To provide a semiconductor device regarding which filling material can be suitably filled in between substrates in a case of disposing a plurality of component parts of the semiconductor device between the substrates, and a manufacturing method of the same. A semiconductor device according to the present disclosure includes a first substrate, a plurality of protruding portions that protrude with respect to a first face of the first substrate, a plurality of types of insulating films that are provided at least between the protruding portions on the first face of the first substrate, a second substrate that is provided facing the first face of the first substrate, and a filling material that is provided between the first substrate and the second substrate, so as to come into contact with the plurality of types of insulating films.

A MEMS transducer package (1) comprises a semiconductor die element (3) and a cap element (23). The semiconductor die element (3) and cap element (23) have mating surfaces (9, 21). The semiconductor die element (3) and cap element (23) are configured such that when the semiconductor die element (3) and cap element (4) are conjoined, a first volume (7, 27) is formed through the semiconductor die element (3) and into the semiconductor cap element (23), and an acoustic channel is formed to provide an opening between a non-mating surface (11) of the semiconductor die element (3) and either a side surface (10, 12) of the transducer package or a non-mating surface (29) of the cap element (23).

A MEMS transducer package (1) is provide having a semiconductor die portion (3) with a thickness bounded by a first surface (9) and an opposite second surface (11). The package further has a transducer element (13) incorporated in the second surface (11) and a die back volume (7) that extends through the thickness of the semiconductor die portion (3) between the first surface (9) and the transducer element (13). The package is completed by a cap portion (23) that abuts the semiconductor die portion (3) at the first surface (9).

A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.