A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.

Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.

An electronic device including a chip, an element structure layer, a redistribution structure layer and a protective layer is provided. The chip has an active surface and a plurality of contacts disposed on the active surface. The element structure layer is disposed adjacent to the active surface and has a switch element. The switch element is electrically connected to the chip through at least one of the plurality of contacts. The redistribution structure layer is disposed adjacent to the active surface and is electrically connected to the chip through at least one of the plurality of contacts. The protective layer includes a first portion and a second portion. The first portion surrounds the chip, and the second portion surrounds the element structure layer and the redistribution structure layer. A manufacturing method of an electronic device is also provided.

Examples herein relate to optoelectronic systems or modules. In particular, implementations herein relate to an optoelectronic module or system that includes a substrate having opposing first and second sides and an optoelectronic component having opposing first and second sides flip chip assembled to the substrate. The optoelectronic component is configured to emit at least one optical signal to the substrate, receive at least one optical signal from the substrate, or both. The optoelectronic system further includes an underfill exclusion structure configured to prevent underfill material dispensed between the optoelectronic component and the substrate from flowing into an optical area or path of the at least one optical signal transmitted between the optoelectronic component and the substrate. The underfill exclusion structure is spaced apart from at least one of the optoelectronic component or the substrate.

A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.

According to one embodiment, a semiconductor device includes a wiring board having a first surface. A first element is disposed on the first surface of the wiring board. A first resin layer covers the first element. A second element is larger than the first element and disposed on the first resin layer. The second element is superposed above the first element. A reinforcement member is disposed at a peripheral portion of the first resin layer and includes an edge disposed inside of the first resin layer. The reinforcement member has an upper surface above the first surface of the wiring board. The reinforcement member has a coefficient of linear expansion lower than the first resin layer. An encapsulating resin material, over the first surface of the wiring board, covers the first element, the second element, the first resin layer, and the reinforcement member.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

In some examples, a device comprises a substrate including a notch formed in a surface of the substrate and a semiconductor die positioned in the notch and including an electrochemical sensor on an active surface of the semiconductor die. The device also comprises a chemically inert member abutting the surface of the substrate and including an orifice in vertical alignment with the electrochemical sensor as a result of the semiconductor die being positioned in the notch. The device also comprises a compressed o-ring seal positioned between the chemically inert member and the active surface of the semiconductor die, the compressed o-ring seal circumscribing the electrochemical sensor.

An electronic component package has an outer edge including a first side and a second side adjacent to each other. The electronic component package includes a first electronic component chip, a second electronic component chip provided at a distance from the first electronic component chip, one or more first terminals disposed along the first side, one or more second terminals disposed along the second side, and one or more first conductors. The one or more first conductors couple the one or more first terminals to the first electronic component chip, with the one or more first terminals being uncoupled to the second electronic component chip.

This thermocompression bonding device is provided with a heating tool (1) and a backup member (3). The backup member (3) has: a support portion (3a) which faces the tip (1a) of the heating tool (1) while first and second members (111, 122) to be joined and a cushioning member (2) are located therebetween, and which supports the first and second members (111, 122) to be joined; and a body portion (3b) provided on the opposite side of the support portion (3a) from the first and second members (111, 122) to be joined. The support portion (3a) is formed so that the heat conductivity thereof is lower than that of the body portion (3b).