A fingerprint sensor is provided. The fingerprint sensor includes a multi-layer printed circuit board (PCB), a fingerprint sensing die and a molding compound. The multi-layer PCB includes a bottom dielectric layer, at least one intermediate dielectric layer disposed on the bottom dielectric layer, a top dielectric layer disposed on the intermediate dielectric layer and a trench. The trench is formed by digging out a portion of the intermediate dielectric layer and a portion of the top dielectric layer. The fingerprint sensing die is disposed in the trench of the multi-layer PCB and mounted on an upper surface of the bottom dielectric layer of the multi-layer PCB. The fingerprint sensing die includes a sensing array capable of sensing fingerprint information of a user. The fingerprint sensing die is covered by the molding compound, and the trench of the multi-layer PCB is filled with the molding compound.

Memory devices are disclosed. A memory device may include an interface region including a first input circuit configured to generate a first output and a second input circuit configured to generate a second output. The interface region may further include a swap circuit positioned between the first input circuit and the second input circuit. The swap circuit may be configured to select the first output for a first internal signal responsive to a first state, and select the second output for the first internal signal responsive to a second, different state. Systems are also disclosed.

A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 m. Corresponding methods of producing multi-chip assemblies are also described.

The present invention relates to a camera module in which a thin camera module can be realized at a low cost and an electronic device. The camera module includes a lens unit that stores a lens that condenses light on a light receiving surface of an image sensor; a rigid substrate on which the image sensor is disposed; and a flexible substrate electrically connected with the rigid substrate, wherein in the case where the light receiving surface of the image sensor locates at the top, the lens unit, the flexible substrate, and the rigid substrate are disposed in this order from the top.

An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

A power semiconductor element is fixed on a die pad of the lead frame. A metal plate is bonded to a lower surface of the die pad via an insulating film. The inner lead etc. are disposed in a cavity between a lower mold and an upper mold and are encapsulated with an encapsulation resin. The lower mold has a stepped portion provided in a bottom surface of the cavity below the inner lead. A height of an upper surface of the stepped portion is larger than a height of an upper surface of the power semiconductor element disposed in the cavity. When an encapsulation resin is injected into the cavity, a lower surface of the metal plate is in contact with the bottom surface of the cavity, and the encapsulation resin flows downward from above the stepped portion toward the upper surface of the power semiconductor element.

An array substrate includes a driver, a glass substrate having a driver mounting section where the driver is mounted, an anisotropic conductive material that is interposed between the driver and driver mounting section so as to electrically connect both and that at least includes a binder made of a thermosetting resin and conductive particles in the binder, and a heat supply part provided on at least the driver mounting section of the glass substrate for supplying heat to the anisotropic conductive material.

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.