An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

A semiconductor device has a semiconductor chip, a signal lead that is arranged in a periphery of the semiconductor chip and has a main surface and a rear surface opposed to the main surface, a wire that electrically connects the semiconductor chip and the main surface of the signal lead, and a sealing body made of sealing resin that seals the semiconductor chip, the signal lead and the wire. The signal lead has, in an extending direction of the signal lead, one end located inside the sealing body, the other end located outside the sealing body, and a wire connection region which is the main surface of the signal lead and to which the wire is connected, and an inner groove is provided in the main surface of the signal lead between the one end and the wire connection region.

A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

The present disclosure provides a semiconductor device. The semiconductor device includes a first chip and a second chip. The second chip is bonded over and electrically connected to the first chip. The second chip includes a seal ring disposed at a periphery of the second chip and within the second chip. From a top view, the second chip includes a first number of sides and the seal ring includes a second number of sides. The first number is greater than four, and the second number is equal to or greater than the first number.

A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.