Camera device structures and methods of manufacturing them are disclosed. A sensor core includes a housing, a camera sensor, an integrated readout circuit, a controller (e.g., a processor unit for image processing), and a ceramic package base. In some examples, the sensor core includes a semiconductor-based micro machined cavity structure (e.g., based on an enclosure formed via the housing) with an integrated lens of the camera core package. The disclosure provides for a camera sensing core package with high reflection coating around walls of the housing, apart from the bottom ceramic base, which allows for maximum or rejection of stray radiation. The thermally balanced properties of the structure provide for improved thermal stability of the camera core of the device, while ensuring near zero thermal gradient across the camera sensor, which may result in improved performance of the camera sensing core.

Void formation in a semiconductor device is to be prevented. The semiconductor device includes a semiconductor element, signal lines, and a protective layer. In the semiconductor device, the semiconductor element is mounted on a substrate. The signal lines in the semiconductor device are connected to the semiconductor element on the substrate. Further, the protective layer in the semiconductor device is provided in an inter-line region interposed between both edges of two adjacent signal lines among the signal lines on the substrate.

One or more embodiments are directed to a semiconductor package that includes transparent encapsulation material and an opaque encapsulation material. In one embodiment, the opaque encapsulation material is thicker than the transparent encapsulation material; however, the outer surfaces of the opaque and the transparent encapsulation materials are coplanar with each other.

The wafer-level manufacturing method makes possible to manufacture ultrathin optical devices such as opto-electronic modules. A clear encapsulation is applied to an initial wafer including active optical components and a wafer-size substrate. Thereon, a photostructurable opaque coating is produced which includes apertures. Then, trenches are produced which extend through the clear encapsulation and establish side walls of intermediate products. Then, an opaque encapsulation is applied to the intermediate products, thus filling the trenches. Cutting through the opaque encapsulation material present in the trenches, singulated optical modules are produced, wherein side walls of the intermediate products are covered by the opaque encapsulation material. The wafer-size substrate can be attached to a rigid carrier wafer during most process steps.

A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

The disclosure discloses an optoelectronic element comprising: an optoelectronic unit comprising a first metal layer, a second metal layer, and an outermost lateral surface; an insulating layer having a first portion overlapping the optoelectronic unit and extending beyond the lateral surface, and a second portion separated from the first portion in a cross-sectional view; and a first conductive layer formed on the insulating layer.

A photoelectric conversion assembly is proposed. The photoelectric conversion module comprises three parts, photoelectric conversion module, a printed circuit board (PCB) and a hybrid cable. The photoelectric conversion module comprises an interposer, at least one optical element configured on the interposer, and an optical bench for the printed circuit board and the interposer configured thereon. Electrical wires are used for coupling to the printed circuit board. An optical ferrule is used for engaging with the photoelectric conversion module and an optical fiber component. A plug is used for electrically connecting the printed circuit board. A first lens array is configured under the interposer. A mirror is configured under the first lens array. A second lens array is configured left side of the mirror.

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50 greater than 2D memory density per die and an ultra high density memory.