According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.

Provided is a technique that enables a passive component to be arranged with a short wiring distance to a power terminal of a semiconductor element mounted on a semiconductor module. In a semiconductor module, a plurality of first connection terminal groups having connection terminals arranged with a first gap therebetween, and a second connection terminal group having connection terminals arranged with a second gap therebetween in a rectangular ring so as to surround the first connection terminal groups, are arranged with a second group gap therebetween that is wider than the first gap and the second gap. In a plan view, a first power terminal of a first semiconductor element overlaps a target terminal group that is one of the first connection terminal groups. In the plan view, a second power terminal of a second semiconductor element overlaps the second connection terminal group.

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor.

A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.

A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.

A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.