A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound.

Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

A lead frame has a first sink, an island, and a control terminal. The lead frame is bent, and at a rear surface, the island is positioned closer to one surface of a resin molded body than the first sink and a passive component mounting portion of the control terminal. A passive component is mounted on the passive component mounting portion of the control terminal through a bonding material, the passive component mounting portion being a part of one surface.

A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

The present invention relates to a conductive paste for bonding comprising 100 parts by weight of the metal powder, 5 to 20 parts by weight of a solvent, and 0.05 to 3 parts by weight of a polymer, wherein the polymer comprises a first polymer and a second polymer, wherein the molecular weight (Mw) of the first polymer is 5,000 to 95,000, and the molecular weight (Mw) of the second polymer is 100,000 to 300,000.

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

A disclosed circuit arrangement includes adhesive transfer tape having a layer of pressure sensitive adhesive (PSA) having a first major surface and a second major surface opposite the first major surface. One or more metal foil pads are attached directly to the second major surface of the layer of PSA. Electrically conductive round wire is attached directly to the second major surface of the layer of PSA. The wire has a round cross-section and one or more portions directly connected to the one or more metal foil pads with one or more weld joints, respectively. An electronic device is attached directly to the second major surface of the layer of PSA and is electrically connected to the one or more portions of the round wire by one or more bond wires, respectively.

A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.