Patent classifications
H01L2924/1531
Structure with controlled capillary coverage
A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.
SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
Semiconductor Package Using A Coreless Signal Distribution Structure
A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.
MODULE
A module includes: a substrate including a first main surface; a first component mounted on the first main surface; a first land electrode provided on the first main surface; a first mold resin that covers at least the first main surface and the first component; a top surface shield film that covers a top surface of the first mold resin; a side surface shield film that covers a side surface of the first mold resin; a first conductor pillar provided in the first mold resin to electrically connect the first land electrode and the top surface shield film; and an upper first bypass conductor provided in the first mold resin to electrically connect the top surface shield film and the side surface shield film.
INTERCONNECT SUBSTRATE HAVING BUFFER MATERIAL AND CRACK STOPPER AND SEMICONDUCTOR ASSEMBLY USING THE SAME
An interconnect substrate includes a lower-modulus buffer material disposed around a thermally conductive base and a higher-modulus crack stopper disposed over the buffer material. By the difference of the elastic modulus between the crack stopper and the buffer material, thermo-mechanical induced stress can be absorbed in the buffer material, and crack propagation would be arrested by the crack stopper to ensure reliability of a routing trace which is deposited on the crack stopper and electrically coupled to vertical connecting elements in the buffer material. Further, the crack stopper can have low dissipation factor to ensure a lower rate of energy loss which is beneficial to high frequency applications.
Electronic assembly and electronic system with impedance matched interconnect structures
Provided is an electronic assembly including (a) an interconnect carrier having an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; (b) a first integrated circuit chip mounted at a first side of the interconnect carrier; (c) a second integrated circuit chip mounted at a second side of the interconnect carrier opposite to the first side; and (d) an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip. The electric interconnection structure extends around the insulating core and includes at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided. Further, there is provided an electronic system comprising such an electronic assembly.
STRUCTURE WITH CONTROLLED CAPILLARY COVERAGE
A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.
Mitigating cracking within integrated circuit (IC) device carrier
Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.
Semiconductor package and fabricating method thereof
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
Micro-transfer printable electronic component
A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display.