Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

A semiconductor device includes a printed circuit board that includes a first electrode, a resin substrate that includes a first face directed toward the printed circuit board, a second electrode formed in a second portion surrounding a first portion of the first face, a second face opposite the first face, and a third electrode formed in a third portion of the second face, the third portion overlapping the first portion in a plan view, a semiconductor chip that includes a coupling terminal joined to the third electrode, a conductive member that is formed between the printed circuit board and the resin substrate and contains a conductive particle and resin, and a solder bump that is formed between the printed circuit board and the resin substrate and is joined to the first electrode and the second electrode.

A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.

A method includes electrically connecting an IC chip module to a motherboard and thermally contacting a heat sink to the IC chip module. The IC chip module includes a carrier comprising a top surface and a bottom surface configured to be electrically connected to the motherboard. The IC chip module includes a stiffening frame attached to the carrier top surface. The stiffening frame includes a base portion that has a central opening and a plurality of opposing sidewalls. The IC chip module further includes a semiconductor chip electrically connected to the carrier top surface and concentrically arranged within the central opening. The IC chip module further includes a first directional heat spreader thermally contacting the semiconductor chip. The first directional heat spreader includes a directionally thermally conductive material arranged to efficiently transfer heat from the semiconductor chip in a first opposing bivector direction towards first opposing sidewalls.